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Complete DDR1/2/3 Memory Power Supply
POWER MANAGEMENT Description
The SC486 is a combination switching regulator and linear source/sink regulator intended for DDR1/2/3 memory systems. The switching regulator is used to generate the supply voltage, VDDQ, for the memory system. It is a pseudo-fixed frequency constant on-time controller designed for high efficiency, superior DC accuracy, and fast transient response. The linear source/sink regulator is used to generate the memory termination voltage, VTT, with the ability to source and sink a 3A peak current. For the VDDQ regulator, the switching frequency is constant until a step in load or line voltage occurs at which time the pulse density, i.e. frequency, will increase or decrease to counter the transient change in output or input voltage. After the transient, the frequency will return to steady-state operation. At lighter loads, the selectable Power-Save Mode enables the PWM converter to reduce its switching frequency and improve efficiency. The integrated gate drivers feature adaptive shoot-through protection and soft-switching. For the VTT regulator, the output voltage tracks VREF, which is 1/2 VDDQ to provide an accurate termination voltage. The VTT output is generated from a 1.2V to VDDQ input by a linear source/sink regulator which is designed for high DC accuracy, fast transient response, and low external component count. Additional features include cycle-by-cycle current limiting, digital soft-start, power good (all VDDQ only) and over-voltage and under-voltage protection (VDDQ and VTT). All 3 outputs (VDDQ, VTT and REF) are actively discharged when VDDQ is disabled, reducing external component count and cost. The SC486 is available in a 24 pin MLPQ 4mmx4mm Lead-free package.
SC486
Features
DDR1, DDR2 and DDR3 compatible Constant on-time controller for fast dynamic response on VDDQ Programmable VDDQ range - 1.5V to 3V 1% Internal Reference (2% System Accuracy) Resistor programmable on time for VDDQ VCCA/VDDP range = 4.5V to 5.5V VBAT range = 2.5V to 25V VDDQ DC current sense using low-side RDS(ON) sensing or external RSENSE in series with low-side FET Cycle-by-cycle current limit for VDDQ Digital soft-start for VDDQ Combined EN and PSAVE pin for VDDQ Over-voltage/under-voltage fault protection for both outputs and PGD output (VDDQ only) Separate VCCA and VDDP supplies VTT/REF range = 0.75V - 1.5V VTT source/sink 3A peak Internal resistor divider for VTT/REF VTT is high impedance in S3 VDDQ, VTT and REF are actively discharged in S4/S5 24-pin MLPQ (4 x 4mm) Lead-free package, fully WEEE and RoHS compliant
Applications
Notebook computers CPU I/O supplies Handheld terminals and PDAs LCD monitors Network power supplies
5VSUS R3 470k VBAT
Typical Application Circuit
VBAT 5VSUS 5VRUN R1 R4 10R C1 no-pop REF R6 10R R9 C6 1uF C7 no-pop C2 R5 1uF R2 10R 11 3 2 6 R7 10R C3 no-pop R8 0R C8 1nF C9 1uF 8 9 10 5 4 14 15 12 13 16 17
U1 VTTEN VDDQS TON FB REF COMP VTTS VCCA VSSA VTT VTT VTTIN VTTIN PGND2 PGND2 PAD
SC486 PGD EN/PSV
7 1 D1
PGOOD
VDDQ
5 BST 24 C4 0.1uF R10 4 3 8
6
C5 10uF
DH ILIM LX
23 21 22
7
L1 VDDQ + C10
VTT VDDQ C11 20uF C12 1uF
DL VDDP PGND1
19 20 18 C13 1uF
2 Q1
1
Revision: September 13, 2006
1
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SC486
POWER MANAGEMENT Absolute Maximum Ratings (10)
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability.
Parameter TON to VSSA DH, BST to PGND1 LX to PGND1 DL, ILIM, VDDP to PGND1 VDDP to DL VTTIN, VTT to PGND2 VTTIN to VTT COMP, EN/PSV, FB, PGD, REF, VCCA, VDDQS, VTTEN, VTTS TO VSSA VCCA to COMP, EN/PSV, FB, REF, VDDQS, VTT, VTTEN, VTTIN, VTTS PGND1 to PGND2, PGND1 to VSSA BST, DH to LX Thermal Resistance Junction to Ambient Operating Junction Temperature Range Storage Temperature Range Peak IR Reflow Temperature, 10s - 40s
Symbol
Maximum -0.3 to +25.0 -0.3 to +30.0 -2.0 to +25.0 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +0.3 -0.3 to +6.0
Units V V V V V V V V V V V C/W C C C
JA TJ TSTG TPKG
29 -40 to +150 -65 to +150 260
Electrical Characteristics
Test Conditions: VBAT = 15V, VCCA = VDDP = VTTEN = EN/PSV = 5V, VDDQ = VTTIN = 1.8V, RTON = 1M
Parameter
Conditions Min
25C Typ Max
-40C to 125C Min Max
Units
Input Supplies VCCA Operating Current VCCA Operating Current, S3 VDDP Operating Current TON Operating Current VTTIN Operating Current VCCA + VDDP + TON Shutdown Current FB > regulation point, IVDDQ = 0A FB > regulation point, IVDDQ = 0A, VTTEN = 0V FB > regulation point, IVDDQ = 0A RTON = 1M IVTT = 0A EN/PSV = VTTEN = 0V 1500 1000 70 15 1 5 5 11 150 2500 A A A A A A
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SC486
POWER MANAGEMENT Electrical Characteristics (Cont.)
Test Conditions: VBAT = 15V, VCCA = VDDP = VTTEN = EN/PSV = 5V, VDDQ = VTTIN = 1.8V, RTON = 1M
Parameter
Conditions Min
25C Typ Max
-40C to 125C Units Min Max
VDDQ Controller FB Error Comparator Threshold(1) On-Time VCCA = 4.5V to 5.5V RTON = 1M RTON = 500k, -10C TA 125C RTON = 500k, -40C TA 125C Minimum Off-Time VDDQS Input Resistance VDDQS Shutdown Discharge Resistance FB Leakage Current VTT Controller COMP Leakage Current REF Source Current REF Output Accuracy REF Shutdown Discharge Resistance VTT Output Accuracy VTT Shutdown Discharge Resistance VTTS Leakage Current Current Sensing ILIM Current Current Comparator Offset Zero-Crossing Threshold VDDQ Fault Protection Current Limit (Positive)(2) PGND1 - LX, RILIM = 5k PGND1 - LX, RILIM = 10k PGND1 - LX, RILIM = 20k Current Limit (Negative) Output Under Voltage Fault Under Voltage Fault Delay
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1.500 460 265
1.485 390 225 225
1.515 530 305 320 550
V
ns
400 150 EN/PSV = GND 22 -1.0
ns k
1.0
A
-1.0 10 IREF = 0 to 10mA EN/PSV = GND -2A < IVTT < 2A EN/PSV = GND 900 22 REF 22 -1.0 -20 882
1.0
A mA
918
mV
+20
mV
1.0
A
10 PGND1 - ILIM PGND1 - LX, EN/PSV = 5V 5
9 -10
11 10
A mV mV
50 100 200 -125 -30 8
35 80 170 -160 -35
65 120 230 -90 -25
mV
PGND1 - LX With respect to internal reference FB forced below UV Vth
3
mV % clks(3)
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SC486
POWER MANAGEMENT Electrical Characteristics (Cont.)
Test Conditions: VBAT = 15V, VCCA = VDDP = VTTEN = EN/PSV = 5V, VDDQ = VTTIN = 1.8V, RTON = 1M
Parameter
Conditions Min
25C Typ Max
-40C to 125C Min Max
Units
VDDQ Fault Protection (Cont.) Under Voltage Blank Time Output Over Voltage Fault Over Voltage Fault Delay PGD Low Output Voltage PGD Leakage Current PGD UV Threshold PGD Fault Delay VCCA Under Voltage VTT Fault Protection Output Under Voltage Fault Output Over Voltage Fault Fault Shutdown Delay Thermal Shutdown (4)(5) Inputs/Outputs Logic Input Low Voltage EN & PSV low VTTEN low Logic Input High Voltage EN high, PSV low VTTEN high Logic Input High Voltage EN/PSV Input Resistance EN high, PSV high Sourcing Sinking Soft Start VDDQ Soft Start Ramp Time VTT Soft Start Ramp Rate (6) Gate Drives Shoot-thru Protection Delay (4)(7) DL Pull-Down Resistance DL Sink Current
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From EN high With respect to internal reference FB forced above OV Vth Sink 1mA FB in regulation, PGD = 5V With respect to internal reference FB forced outside PGD window Falling edge, hysteresis 100mV
440 +16 5 0.4 1 -10 5 4.0 3.7 4.3 -12 -8 +12 +20
clks(3) % s V A % s V
VTT w/rt REF VTT w/rt REF VTT outside UV/OV window
-12 +12 50 160
-16 +8
-8 +16
% % s
150
170
C
1.2 0.6 2.0 2.4 3.1 1.5 1.0
V
V
V M
EN/PSV high to PGD high
440 6
clks(3) mV/s
DH or DL rising DL low VDL = 2.5V
4
30 0.8 3.1 1.6
ns A
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SC486
POWER MANAGEMENT Electrical Characteristics (Cont.)
Test Conditions: VBAT = 15V, VCCA = VDDP = VTTEN = EN/PSV = 5V, VDDQ = VTTIN = 1.8V, RTON = 1M
Parameter
Conditions Min
25C Typ Max
-40C to 125C Min Max
Units
Gate Drives (Cont.) DL Pull-Up Resistance DL Source Current DH Pull-Down Resistance DH Pull-Up Resistance(8) DH Sink/Source Current VTT Pull-Up Resistance VTT Pull-Down Resistance VTT Peak Sink/Source Current (9) DL high VDL = 2.5V DH low, BST - LX = 5V DH high, BST - LX = 5V VDH = 2.5V VTTS < REF VTTS > REF 2 1.3 2 2 1.3 0.25 0.25 3.6 2.0 0.45 0.45 4 4 4 A A A
Notes: (1) The output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the ripple voltage. (2) Using a current sense resistor, this measurement relates to PGND1 minus the voltage of the source on the low-side MOSFET. (3) clks = switching cycles, consisting of one high side and one low side gate pulse. (4) Guaranteed by design. (5) Thermal shutdown latches both outputs (VTT and VDDQ) off, requiring VCCA or EN/PSV cycling to reset. (6) VTT soft start ramp rate is 6mV/s typical unless VDDQ/2 ramp rate is slower. If this is true, VTT soft start ramps at 6mV/s (typ.) until it reaches VDDQ/2, and then tracks it. (7) See Shoot-Through Delay Timing Diagram below. (8) Semtech's SmartDriverTM FET drive first pulls DH high with a pull-up resistance of 10 (typ.) until LX = 1.5V (typ.). At this point, an additional pull-up device is activated, reducing the resistance to 2 (typ.). This negates the need for an external gate or boost resistor. (9) Provided operation below TJ(MAX) is maintained. (10) This device is ESD sensitive. Use of standard ESD handling precautions is required.
Shoot-Through Delay Timing Diagram
LX
DH
DL DL tplhDL tplhDH
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SC486
POWER MANAGEMENT Pin Configuration
Top View
Ordering Information
DEVICE SC486IMLTRT(2) S C 486E V B PACKAGE(1) MLPQ-24 Evaluation Board
Note: (1) Only available in tape and reel packaging. A reel contains 3000 devices. (2) Lead-free product. This product is fully WEEE and RoHS compliant.
(MLPQ-24)
Pin Descriptions
Pin # 1 Pin Name EN/PSV Pin Function Enable/Power Save input pin. Tie to ground to disable VDDQ. Tie to +5V to enable VDDQ and activate PSAVE mode. Float to enable VDDQ and activate continous conduction mode. If floated, bypass to VSSA with a 10nF capacitor. This pin is used to sense VBAT through a pullup resistor, RTON, and set the top MOSFET ontime. Bypass this pin with a 1nF capacitor to VSSA. Sense pin for VDDQ. Used to set the on-time for the top MOSFET and also to set VREF/VTT. Use a 10/1F RC filter from VDDQ to VSSA. Ground reference for analog circuitry. Connect directly to R9, C6, C7, C8, and C9 (see Page 1) on same side of PCB as I.C. Connect to thermal pad. Supply voltage input for the analog supply. Use a 10/1F RC filter from 5VSUS to VSSA. Feedback input for VDDQ. Connect to a resistor divider from the output to VSSA to set the output voltage between 1.5V and VCCA. Power good output for VDDQ. PGD is low if VDDQ is outside the power good thresholds. This pin is an open drain NMOS output and requires an external pull-up resistor. Reference output. An internal resistor divider from VDDQS sets this voltage to 50% VDDQ (nominal). Bypass this pin with a series 10/1F to VSSA. The connection to R6 (see Page 1) should be made close to pin 8. Error amplifier compensation for VTT output. Sense pin for VTT. Connect to VTT at the load. Enable pin for VTT. Pull this pin low to disable VTT (VREF remains present as long as VDDQ is present). Input supply for the high side switch for VTT regulator. Decouple this pin with a 1F capacitor to PGND2.
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2 3 4 5 6 7 8
TON VDDQS VSSA VC C A FB PGD REF
9 10 11 12,13
COMP VTTS VTTEN VTTIN
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SC486
POWER MANAGEMENT Pin Descriptions (Cont)
14,15 16,17 18 19 20 21 22 23 24 VTT PGND2 PGND1 DL VD D P ILIM LX DH BST THERMAL PAD Output of the linear regulator. Decouple with two (minimum) 10F ceramic capacitors to PGND2, locating them directly across pins 14, 15, 16, and 17. Power ground for VTT output. Connect to thermal pad and ground plane. Power ground for VDDQ output. Connect to thermal pad and ground plane. Gate drive output for the low side MOSFET switch. +5V supply voltage input for the VDDQ gate drivers. Current limit input pin. Connect to drain of low-side MOSFET for RDS(on) sensing or the source for resistor sensing through a threshold sensing resistor. Phase node - the junction between the top and bottom FETs and the output inductor. Gate drive output for the high side MOSFET switch. Boost capacitor connection for the high side gate drive. Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected internally.
Marking Information
Top View
Part Number yyww = Date Code (Example: 0012) xxxxx = Semtech Lot No. (Example: E9010 xxx 1-1)
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SC486
POWER MANAGEMENT Block Diagram
Figure 1 - SC486 Block Diagram
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SC486
POWER MANAGEMENT Enable Control Logic
Enable Pin Status EN/PSV (1) 0 0 1 1 V TTE N 0 1 0 1 VD D Q OFF, Discharged OFF, Discharged ON ON
(2)(3)
Output Status V TT OFF, Discharged (2) OFF, Discharged (2) OFF, High Impedance ON R EF OFF, Discharged
(2)
(2)(3)
OFF, Discharged (2) ON ON
Notes: (1) EN/PSV = 1 = EN/PSV high or floating. (2) Discharge resistance = 22 typ. (3) VDDQ is discharged via R4 (see Page 1) so this resistance must be added when calculating discharge times.
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SC486
POWER MANAGEMENT Application Information
+5V Bias Supply The SC486 requires an external +5V bias supply in addition to the battery. This is connected to VDDP for the VDDQ switching drive power and via an RC filter to VCCA for the chip supply. If stand-alone capability is required, the +5V supply can be generated with an external linear regulator. VTTIN Supply The VTTIN pins provide the input power for the high side (sourcing) section of the VTT LDO. These pins should be decoupled to PGND2. If the output capacitors for the input supply for VTTIN (whether it is VDDQ or a different supply) are not close to the chip, additional local bulk capacitance may be required. Grounding The SC486 has three ground connections, VSSA, PGND1 and PGND2 (2 pins). These should all be starred together at the thermal pad under the device, which in turn will be connected to the ground plane using multiple vias. VSSA is the controller ground reference, to avoid interference between the power and reference sections. PGND1 is the power ground connection for the switching controller for VDDQ. PGND2 is the power ground connection for the sink-source LDO for VTT. All external components referenced to VSSA in the schematic should be connected directly to the VSSA trace. The supply decoupling capacitor should be tied between VCCA and VSSA. A 10 resistor should be used to decouple the VCCA supply from the main VDDP supply. The VDDP input provides power to the upper and lower gate drivers of the switching supply. A decoupling capacitor with no series resistor between VDDP and 5V is required. See layout guidelines for more details. Pseudo-fixed Frequency Constant On-Time PWM Controller (VDDQ) The PWM control architecture consists of a constant ontime, pseudo fixed frequency PWM controller (see Figure 1, SC486 Block Diagram). The output ripple voltage developed across the output filter capacitor's ESR provides the PWM ramp signal eliminating the need for a current sense resistor. The high-side switch on-time is determined by a one-shot whose period is directly proportional to output voltage and inversely proportional to input voltage. A second one-shot sets the minimum off-time which is typically 400ns.
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On-Time One-Shot (tON) The on-time one-shot comparator has two inputs. One input looks at the output voltage, while the other input samples the input voltage and converts it to a current. This input voltage-proportional current is used to charge an internal on-time capacitor. The on-time is the time required for the voltage on this capacitor to charge from zero volts to VOUT, thereby making the on-time of the high-side switch directly proportional to output voltage and inversely proportional to input voltage. This implementation results in a nearly constant switching frequency without the need for a clock generator.
V t ON = 3.3 x10 -12 * (R TON + 37 x10 3 ) * OUT + 50ns V IN
RTON is a resistor connected from the input supply to the TON pin. Due to the high impedance of this resistor, the TON pin should always be bypassed to VSSA using a 1nF ceramic capacitor. EN/PSV: Enable, PSAVE and Soft Discharge The EN/PSV pin enables the VDDQ (2.5V or 1.8V) output and the REF output. VTTEN enables the VTT (1.25V or 0.9V) output provided that VDDQ is present. See Enable Control Logic on Page 9. When EN/PSV is pulled high the VDDQ controller is enabled and power save will also be enabled. When the EN/PSV pin is tri-stated (allowed to float, a 10nF capacitor is required in this instance), an internal pull-up will activate the VDDQ controller and power save will be disabled. If PSAVE is enabled, the SC486 PSAVE comparator will look for the inductor current to cross zero on eight consecutive switching cycles by comparing the phase node (LX) to PGND1. Once observed, the controller will enter power save and turn off the low side MOSFET when the current crosses zero. To improve lightload efficiency and add hysteresis, the on-time is increased by 50% in power save. The efficiency improvement at light-loads more than offsets the disadvantage of slightly higher output ripple. If the inductor current does not cross zero on any switching cycle, the controller will immediately exit power save. Since the controller counts zero crossings, the converter can sink current as long as the current does not cross zero on eight consecutive cycles. This allows the output voltage to recover quickly in response to negative load steps even when psave is enabled.
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SC486
POWER MANAGEMENT
EN/PSV: Enable, PSAVE and Soft Discharge (Cont.) If the EN/PSV pin is pulled low, all three outputs will be shut down and discharged using switches with a nominal resistance of 22 Ohms, regardless of the state of the VTTEN pin. This will ensure that the outputs will be in a defined state next time they are enabled and also ensure, since this is a soft discharge, that there are no dangerous negative voltage excursions to be concerned about. In order for the soft discharge circuitry to function correctly, the chip supply must be present. VTTEN The VTTEN pin is used to enable the VTT regulator only. Pulling it high enables the regulator as long as VDDQ/ REF are present. Pulling VTTEN low while EN/PSV is floating or high will turn off the VTT regulator and leave it in a high-impedance state for S3 mode (VDDQ and REF present, VTT high-Z). VDDQ Output Voltage Selection and Output Sense The output voltage is set by the feedback resistors R5 & R9 of Figure 2 below. The internal reference is 1.5V, so the voltage at the feedback pin will match the 1.5V reference. Therefore the output can be set to a minimum of 1.5V. The equation for setting the output voltage is: VDDQ Current Limit Circuit Current limiting of the SC486 can be accomplished in two ways. The on-state resistance of the low-side MOSFETs can be used as the current sensing element or sense resistors in series with the low-side sources can be used if greater accuracy is desired. R DS(ON) sensing is more efficient and less expensive. In both cases, the RILIM resistors between the ILIM pin and LX pin set the over current threshold. This resistor RILIM is connected to a 10A current source within the SC486 which is turned on when the low side MOSFET turns on. When the voltage drop across the sense resistor or low side MOSFET equals the voltage across the RILIM resistor, positive current limit will activate. The high side MOSFET will not be turned on until the voltage drop across the sense element (resistor or MOSFET) falls below the voltage across the RILIM resistor. In an extreme overcurrent situation, the top MOSFET will never turn back on and eventually the part will latch off due to output undervoltage (see Output Undervoltage Protection). The current sensing circuit actually regulates the inductor valley current (see Figure 3). This means that if the current limit is set to 10A, the peak current through the inductor would be 10A plus the peak ripple current, and the average current through the inductor would be 10A plus 1/2 the peak-to-peak ripple current. The equations for setting the valley current and calculating the average current through the inductor are shown overleaf.
R5 VOUT = 1 + * 1.5 R8 VDDQS is used to sense the output voltages for the ontime one-shot, tON, and also to generate REF, which is 1/ 2 of VDDQ. An RC filter consisting of 10 and 1F from VDDQ to VSSA is required (R4 and C2 in Figure 2) to filter switching frequency ripple.
VBAT 5VSUS 5VRUN
5VSUS R3 470k
VBAT
R1 R4 C1 no-pop REF R6 10R R9 C6 1uF C7 no-pop R7 10R C3 no-pop R8 0R C8 1nF 10R C2 R5 1uF
R2 10R 11 3 2 6 8 9 10 5 C9 1uF 4 14 15 12 13 16 17
U1 VTTEN VDDQS TON FB REF COMP VTTS
SC486 PGD EN/PSV
7 1 D1
PGOOD
VDDQ
5 BST 24 C4 0.1uF DH 23 21 22 R10 4 3 8
6
C5 10uF
VCCA VSSA VTT VTT VTTIN VTTIN PGND2 PGND2
ILIM LX
7
L1 VDDQ + C10
VTT VDDQ C11 20uF C12 1uF
DL VDDP PGND1
19 20 18 C13 1uF
2 Q1
1
Figure 2
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SC486
POWER MANAGEMENT
VDDQ Current Limit Circuit (Cont.) Power Good Output The VDDQ output has its own power good output. Power good is an open-drain output and requires a pull-up resistor. When VDDQ is 16% above or 10% below its set voltage, PGD gets pulled low. It is held low until the output voltage returns to within these thresholds. PGD is also held low during start-up and will not be allowed to transition high until soft start is over (440 switching cycles) and the output reaches 90% of its set voltage. There is a 5s delay built into the PGD circuitry to prevent false transitions. Output Overvoltage Protection VDDQ: when the output exceeds 16% of its set voltage the low-side MOSFET is latched on. It stays latched on and the controller is latched off until reset (see below). There is a 5s delay built into the OV protection circuit to prevent false transitions. An OV fault in VDDQ will cause REF and VTT to turn off (high-Z) also when VDDQ drops below 0.5V. Note: to reset from any fault, VCCA or EN/PSV must be toggled. VTT: when the output exceeds 12% of its set voltage the output is latched in a tri-stated condition (high-Z). The controller stays latched off until reset (see below). There is a 50s delay built into the OV protection circuit to prevent false transitions. An OV fault in VTT will not affect VDDQ or REF. To reset VTT from a fault, VCCA or VTTEN or EN/PSV must be toggled. Output Undervoltage Protection VDDQ: when the output is 30% below its set voltage the output is latched in a tri-stated condition. It stays latched and the controller is latched off until reset (see below). There is a 5s delay built into the UV protection circuit to prevent false transitions. An UV fault in VDDQ will cause REF and VTT to turn off (high-Z) also when VDDQ drops below 0.5V. VTT: when the output is 12% below its set voltage the output is latched in a tri-stated condition (high-Z). The controller stays latched off until reset (see below). There is a 50s delay built into the UV protection circuit to prevent false transitions. An UV fault in VTT will not affect VDDQ or REF. To reset VTT from a fault, VCCA or VTTEN or EN/PSV must be toggled.
INDUCTOR CURRENT
IPEAK ILOAD ILIMIT
TIME Valley Current-Limit Threshold Point
Figure 3: Valley Current Limiting The equation for the current limit threshold is as follows:
ILIMIT = 10e -6 *
RILIM A R SENSE
Where (referring to Figure 2) RILIM is R10 and RSENSE is the RDS(ON) of the bottom of Q1. For resistor sensing, a sense resistor is placed between the source of Q1 and PGND1. The current through the source sense resistor develops a voltage that opposes the voltage developed across RILIM. When the voltage developed across the RSENSE resistor reaches the voltage drop across RILIM, a positive over-current exists and the high side MOSFET will not be allowed to turn on. When using an external sense resistor RSENSE is the resistance of the sense resistor. The current limit circuitry also protects against negative over-current (i.e. when the current is flowing from the load to PGND1 through the inductor and bottom MOSFET). In this case, when the bottom MOSFET is turned on, the phase node, LX, will be higher than PGND initially. The SC486 monitors the voltage at LX, and if it is greater than a set threshold voltage of 125mV (nom.) the bottom MOSFET is turned off. The device then waits for approximately 2.5s and then DL goes high for 300ns (typ.) once more to sense the current. This repeats until either the over-current condition goes away or the part latches off due to output overvoltage (see Output Overvoltage Protection).
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SC486
POWER MANAGEMENT
POR, UVLO and Softstart An internal power-on reset (POR) occurs when VCCA exceeds 3V, starting up the internal biasing. VCCA undervoltage lockout (UVLO) circuitry inhibits the whole controller until VCCA rises above 4.2V. At this time the UVLO circuitry enables the REF buffer, resets the fault latch and soft start timer, and allows switching to occur, if enabled. Switching always starts with DL to charge up the BST capacitor. With the softstart circuit (automatically) enabled, it will progressively limit the output current (by limiting the current out of the ILIM pin) over a predetermined time period of 440 switching cycles. The ramp occurs in four steps: 1) 110 cycles at 25% ILIM with double minimum off-time (for purposes of the on-time one-shot, there is an internal positive offset of 120mV to VOUT during this period to aid in startup) 2) 110 cycles at 50% ILIM with normal minimum off-time 3) 110 cycles at 75% ILIM with normal minimum off-time 4) 110 cycles at 100% ILIM with normal minimum off-time. At this point the output undervoltage and power good circuitry is enabled. When VDDQ reaches 0.5V, the REF output is enabled and rises to VDDQS/2. VTT attempts to track REF but its own soft start circuitry will limit its rise rate to 6mV/s. If VDDQ is rising slow enough, VTT will rise at 6mV/s until it reaches VDDQ/2 and then track VDDQ. There is 100mV of hysteresis built into the UVLO circuit and when VCCA falls to 4.1V (nom.) the output drivers are shut down and tri-stated. MOSFET Gate Drivers The DH and DL drivers are optimized for driving moderate-sized high-side, and larger low-side power MOSFETs. An adaptive dead-time circuit monitors the DL output and prevents the high-side MOSFET from turning on until DL is fully off (below ~1V). Semtech's SmartDriverTM FET drive first pulls DH high with a pull-up resistance of 10 (typ.) until LX = 1.5V (typ.). At this point, an additional pull-up device is activated, reducing the resistance to 2 (typ.). This negates the need for an external gate or boost resistor. The adaptive dead-time circuit also monitors the phase node, LX, to determine the state of the high side MOSFET, and prevents the lowside MOSFET from turning on until DH is fully off (LX below ~1V). Be sure to have low resistance and low inductance between the DH and DL outputs to the gate of each MOSFET.
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DDR Reference Buffer The reference buffer is capable of driving 10mA and sinking 25A. Since the output is class A, if additional sinking is required an external pulldown resistor can be added. Make sure that the ground side of this pulldown is tied to VSSA. As with most opamps, a small resistor is required when driving a capacitive load. To ensure stability use either a 10 resistor in series with a 1F capacitor or a 100 resistor in series with a 0.1F capacitor from REF to VSSA. VTT Sink/Source Output The VTT regulator is a sink/source LDO capable of supplying peak currents up to 3.6A. It has been designed to operate with output capacitances as low as 20F (two 10F 1210 ceramic capacitors). These capacitors need to be placed directly across the VTT and PGND2 pins to minimize parasitic resistance and inductance. Additional ceramic capacitors may be used to improve transient response further if desired. The VTT input requires a 1F ceramic capacitor for bypass purposes located right at the pin. If the output capacitors for the power rail being used for VTTIN are far from the part then additional bulk capacitance of two 10F ceramic capacitors should be added. COMP Pin The VTT COMP pin is provided to permit the addition of a zero into the VTT control loop by adding a resistor (less than 100) between COMP and REF and a capacitor from COMP to VTTS (R7 and C3 in Figure 2). The zero frequency should be set to approximately 10 times the unity gain bandwidth, which is ~1MHz, therefore fZ should be ~10MHz. fZ is given by the following equation:
fZ =
1 2* *R * C
Typically this compensation will not be required, so C3 should be no-pop and R7 should be 0 or 10. VTTS Pin The VTTS pin is used to kelvin sense the VTT output. An RC filter (with R from VTT to VTTS less than 100 and C from VTTS to VSSA, R8 and C7 in Figure 2) may be used to compensate any zeroes created by less than optimal ESR at the output. With the recommended output capacitors they are not necessary so R should be 0 and C should be no-pop.
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SC486
POWER MANAGEMENT
Dropout Performance VDDQ: the output voltage adjust range for continuous-conduction operation is limited by the fixed 550ns (maximum) minimum off-time one-shot. For best dropout performance, use the slowest on-time setting of 200kHz. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. The IC duty-factor limitation is given by:
DUTY =
t ON( MIN ) t ON( MIN )
VBAT = 6V, then the measured DC output will be 2.525V. If the ripple increases to 80mV with VBAT = 25V, then the measured DC output will be 2.540V. The output inductor value may change with current. This will change the output ripple and thus the DC output voltage. It will not change the frequency. Switching frequency variation with load can be minimized by choosing MOSFETs with lower RDS(ON). High RDS(ON) MOSFETs will cause the switching frequency to increase as the load current increases. This will reduce the ripple and thus the DC output voltage. SC486 System DC Accuracy (VTT Sink/Source LDO) The VTT LDO is designed to track the voltage at REF, with a guaranteed DC accuracy of REF +/-20mV for -2A to +2A. Thus the DDR/DDR2 absolute requirement of +/-40mV including transients is an easy goal to achieve provided that careful attention is paid during board layout to reduce parasitic ESR/ESL. DDR Supply Selection The SC486 can be configured so that the VTT supply can be generated from the VDDQ supply, or from an alternate supply (usually lower to minimize power dissipation). If the VTT LDO is going to be powered from the VDDQ output, the electrical design of the VDDQ output needs to be for IDDQ(MAX) + ITT(MAX).
+ t OFF(MAX )
Be sure to include inductor resistance and MOSFET onstate voltage drops when performing worst-case dropout duty-factor calculations. VTT: the minimum input voltage allowed to be applied to VTTIN (if a supply other than VDDQ is being used) should be determined using the required maximum output current and the maximum VTT pull-up resistance, 0.45. The minimum VTTIN for a given VTT and ITT can be calculated as follows:
VTTIN(MIN) = VTT + ITT * RPULLUP(MAX)
For example: for VTT = 0.9V out and ITT = 1.25A, VTTIN can go as low as 1.463V. SC486 System DC Accuracy (VDDQ Controller) Two IC parameters affect system DC accuracy, the error comparator threshold voltage variation and the switching frequency variation with line and load. The error comparator threshold does not drift significantly with supply and temperature. Thus, the error comparator contributes 1% or less to DC system inaccuracy. Board components and layout also influence DC accuracy. The use of 1% feedback resistors contribute 1%. If tighter DC accuracy is required use 0.1% feedback resistors. The on-pulse in the SC486 is calculated to give a pseudo fixed frequency. Nevertheless, some frequency variation with line and load can be expected. This variation changes the output ripple voltage. Because constant on-time regulators regulate to the valley of the output ripple, 1/2 of the output ripple appears as a DC regulation error. For example, if the feedback resistors are chosen to divide down the output by a factor of five, the valley of the output ripple will be 2.5V. If the ripple is 50mV with
2006 Semtech Corp. 14
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SC486
POWER MANAGEMENT
Design Procedure - VDDQ Controller Prior to designing an output and making component selections, it is necessary to determine the input voltage range and the output voltage specifications. For purposes of demonstrating the procedure an 8A VDDQ output being used to power VTT at +/-2A for a total IDDQ of 10A will be designed. The maximum input voltage (VBAT(MAX)) is determined by the highest AC adaptor voltage. The minimum input voltage (V BAT(MIN)) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. For the purposes of this design example we will use a VBAT range of 9V to 19.2V. Four parameters are needed for the output: 1) nominal output voltage, VOUT (for DDR2 this is 1.8V) 2) static (or DC) tolerance, TOLST (we will use +/-4% for this design ) 3) transient tolerance, TOLTR and size of transient (we will use +/-100mV for this design). 4) maximum output current, IOUT (we are designing for 10A) Switching frequency determines the trade-off between size and efficiency. Increased frequency increases the switching losses in the MOSFETs, since losses are a function of VIN2. Knowing the maximum input voltage and budget for MOSFET switches usually dictates where the design ends up. The default RtON value of 715k is suggested as a starting point, but it is not set in stone. The first thing to do is to calculate the on-time, tON, at VBAT(MIN) and VBAT(MAX), since this depends only upon VBAT, VOUT and RtON.
VOUT -9 t ON _ VBAT(MIN) = 3.3 * 10 -12 * (R tON + 37 * 103 ) * + 50 * 10 s VBAT (MIN)
and
fSW _ VBAT (MAX ) =
(V
VOUT Hz BAT ( MAX ) * t ON _ VBAT ( MAX ) )
tON is generated by a one-shot comparator that samples VBAT via RtON, converting this to a current. This current is used to charge an internal 3.3pF capacitor to VOUT. The equations above reflect this along with any internal components or delays that influence tON. For our DDR2 VDDQ example we select RtON = 715k: tON_VBAT(MIN) = 546ns and tON_VBAT(MAX) = 283ns fSW_VBAT(MIN) = 366kHz and fSW_VBAT(MAX) = 332kHz Now that we know tON we can calculate suitable values for the inductor. To do this we select an acceptable inductor ripple current. The calculations below assume 50% of IOUT which will give us a starting place.
L VBAT (MIN) = (VBAT (MIN) - VOUT ) *
and
t ON _ VBAT (MIN)
OUT
(0.5 * I )
H
L VBAT (MAX ) = (VBAT (MAX ) - VOUT ) *
t ON _ VBAT (MAX )
(0.5 * I )
OUT
H
For our DDR2 VDDQ example: LVBAT(MIN) = 0.8H and LVBAT(MAX) = 1.0H We will select an inductor value of 1.5H to reduce the ripple current, which can be calculated as follows:
IRIPPLE _ VBAT (MIN) = (VBAT (MIN) - VOUT ) *
and
t ON _ VBAT (MIN) L
A P -P
and
t ON _ VBAT (MAX ) VOUT -9 = 3.3 * 10 -12 * (R tON + 37 * 10 3 ) * + 50 * 10 s VBAT(MAX )
IRIPPLE _ VBAT (MAX ) = (VBAT (MAX ) - VOUT ) *
t ON _ VBAT (MAX ) L
A P -P
From these values of tON we can calculate the nominal switching frequency as follows:
fSW _ VBAT (MIN ) =
VOUT (VBAT (MIN) * t ON _ VBAT (MIN) )Hz
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POWER MANAGEMENT
Design Procedure (Cont.) For our DDR2 VDDQ example: IRIPPLE_VBAT(MIN) = 2.62AP-P and IRIPPLE_VBAT(MAX) = 3.28AP-P From this we can calculate the minimum inductor current rating for normal operation: RESR_TR(MAX) = 5.5m for a full 10A load transient We will select a value of 7.5m maximum for our design, which would be achieved by using two 15m output capacitors in parallel. Note that for constant-on converters there is a minimum ESR requirement for stability which can be calculated as follows:
IINDUCTOR (MIN) = IOUT (MAX ) +
IRIPPLE _ VBAT (MAX ) 2
A (MIN)
For our DDR2 VDDQ example: IINDUCTOR(MIN) = 11.6A(MIN) Next we will calculate the maximum output capacitor equivalent series resistance (ESR). This is determined by calculating the remaining static and transient tolerance allowances. Then the maximum ESR is the smaller of the calculated static ESR (R ESR_ST(MAX)) and transient ESR (R ESR_TR(MAX)):
RESR (MIN ) =
3 2 * * COUT * fSW
This criteria should be checked once the output capacitance has been determined. Now that we know the output ESR we can calculate the output ripple voltage:
VRIPPLE _ VBAT(MAX) = RESR * IRIPPLE _ VBAT(MAX) VP -P
and
RESR _ ST (MAX ) =
(ERR
ST
- ERRDC ) * 2
IRIPPLE _ VBAT (MAX )
Ohms
VRIPPLE _ VBAT(MIN) = RESR * IRIPPLE _ VBAT(MIN) VP -P
For our DDR2 VDDQ example: VRIPPLE_VBAT(MAX) = 25mVP-P and VRIPPLE_VBAT(MIN) = 20mVP-P Note that in order for the device to regulate in a controlled manner, the ripple content at the feedback pin, VFB, should be approximately 15mVP-P at minimum V BAT , and worst case no smaller than 10mV P-P . If VRIPPLE_VBAT(MIN) is less than 15mVP-P the above component values should be revisited in order to improve this. A small capacitor, CTOP, may be required in parallel with the top feedback resistor, RTOP, in order to ensure that VFB is large enough. CTOP should not be greater than 100pF. The value of CTOP can be calculated as follows, where RBOT is the bottom feedback resistor. Firstly calculating the value of ZTOP required:
Where ERRST is the static output tolerance and ERRDC is the DC error. The DC error will be 1% plus the tolerance of the feedback resistors, thus 2% total for 1% feedback resistors. For our DDR2 VDDQ example: ERRST = 72mV and ERRDC = 36mV, therefore RESR_ST(MAX) = 22m
RESR _ TR (MAX ) =
(ERR
TR
- ERR DC )
I IOUT + RIPPLE _ VBAT (MAX ) 2
Ohms
Where ERRTR is the transient output tolerance. Note that this calculation assumes that the worst case load transient is full load. For half of full load, divide the IOUT term by 2. For our DDR2 VDDQ example: ERRTR = 100mV and ERRDC = 36mV, therefore
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Z TOP =
RBOT * (VRIPPLE _ VBAT (MIN) - 0.015 )Ohms 0.015
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POWER MANAGEMENT
Design Procedure (Cont.) Secondly calculating the value of CTOP required to achieve this:
1 1 - Z TOP R TOP F = 2 * * fSW _ VBAT (MIN)
calculated by substituting the desired current for the IOUT term. For our DDR2 VDDQ example: COUT(MIN) = 839F. We will select 440F, using two 220F, 15m capacitors in parallel, which will be good for load release steps of up to 6.7A. Next we calculate the RMS input ripple current, which is largest at the minimum battery voltage:
C TOP
For our DDR2 VDDQ example we will use RTOP = 4.64k and RBOT = 23.2k, therefore VFB_VBAT(MIN) = 16.7mVP-P - good No additional capacitance is required, however a no-pop space is recommended to allow for adjustment once the design is complete, laid out and built. Next we need to calculate the minimum output capacitance required to ensure that the output voltage does not exceed the transient maximum limit, POSLIMTR, starting from the actual static maximum, VOUT_ST_POS, when a load release occurs:
IIN(RMS ) = VOUT * (VBAT (MIN) - VOUT ) *
For our DDR2 VDDQ example: IIN(RMS) = 4ARMS
IOUT VBAT _ MIN
A RMS
VOUT _ ST _ POS = VOUT + ERRDC V
For our DDR2 VDDQ example: VOUT_ST_POS = 1.836V
POSLIM TR = VOUT * TOL TR V
Input capacitors should be selected with sufficient ripple current rating for this RMS current, for example a 10F, 1210 size, 25V ceramic capacitor can handle approximately 3A RMS . Refer to manufacturer's data sheets. Finally, we calculate the current limit resistor value. As described in the current limit section, the current limit looks at the "valley current", which is the average output current minus half the ripple current. We use the maximum room temperature specification for MOSFET RDS(ON) at VGS = 4.5V for purposes of this calculation:
Where TOLTR is the transient tolerance. For our DDR2 VDDQ example: POSLIMTR = 1.900V The minimum output capacitance is calculated as follows:
I IOUT + RIPPLE _ VBAT (MAX ) 2 =L* F 2 2 POSLIM TR - VOUT _ ST _ POS
2
IVALLEY = IOUT -
IRIPPLE _ VBAT (MIN) 2
A
The ripple at low battery voltage is used because we want to make sure that current limit does not occur under normal operating conditions.
RILIM = (IVALLEY * 1.2) *
RDS( ON) * 1.4 10 * 10 - 6
Ohms
C OUT (MIN)
(
)
For our DDR2 VDDQ example RDS(ON) = 9m: IVALLEY = 8.69A and RILIM = 13.1k We select the next lowest 1% resistor value: 13.0k
This calculation assumes the absolute worst case condition of a full-load to no load step transient occurring when the inductor current is at its highest. The capacitance required for smaller transient steps my be
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SC486
POWER MANAGEMENT
Thermal Considerations The junction temperature of the device may be calculated as follows:
TJ = TA + PD * JA C
Inserting the following values for VBAT(MIN) condition (since this is the worst case condition for power dissipation in the controller) as an example): TA = 85C JA = 29C/W VCCA = VDDP = 5V IVCCA = 2500A (data sheet maximum) IVDDP = 150A (data sheet maximum) Vg = 5V Qg = 60nC f = 366kHz VBAT(MIN) = 8V VBST(MIN) = VBAT(MIN)+VDDP = 13V D1(MIN) = 1.8/8 = 0.225 VDDQ = VTTIN = 1.8V VTT = 0.9V ITT = 1.2A gives us:
Where: TA = ambient temperature (C) PD = power dissipation in (W) JA = thermal impedance junction to ambient from absolute maximum ratings (C/W) The power dissipation may be calculated as follows, assuming that VTT spends 50% of its time sourcing current and 50% sinking:
PD = VCCA * IVCCA + VDDP * IVDDP + (VTTIN - VTT ) * ITT + Vg * Q g * f + VBST * 1mA * D W
PD = 5 * 2500e -6 + 5 * 150e -6 + 5 * 60e -9 * 366e 3 + 13 * 1mA * 0.225 + (1.8 - 0.9 ) * 1.2 = 1.206 W
and therefore:
TJ = 85 + 1.206 * 29 = 120C
Where: VCCA = chip supply voltage (V) IVCCA = operating current (A) VDDP = gate drive supply voltage (V) IVDDP = gate drive operating current (A) Vg = gate drive voltage, typically 5V (V) Qg = FET gate charge, from the FET datasheet (C) f = switching frequency (Hz) VBST = boost pin voltage during tON (V) D = duty cycle VTTIN = input voltage for VTT LDO (V) ITT = maximum VTT current (A)
As can be seen, the heating effects due to internal power dissipation are dominated by the VTT LDO, but they can be managed comfortably by the MLPQ-24 package which is heatsunk to the ground plane using 4 vias from its thermal pad.
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SC486
POWER MANAGEMENT
Layout Guidelines One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and maximize heat dissipation. The IC ground reference, VSSA, should be connected to PGND1 and PGND2 as a star connection at the thermal pad, which in turn is connected using 4 vias to the ground plane. All components that are referenced to VSSA should connect to it directly on the chip side, and not through the ground plane. VDDQ: the feedback trace must be kept far away from noise sources such as switching nodes, inductors and gate drives. Route the feedback trace in a quiet layer if possible from the output capacitor back to the chip. Chip supply decoupling capacitors (VCCA, VDDP) should be located next to the pins (VCCA and VSSA, VDDP and PGND1) and connected directly to them on the same side. VTT: output capacitors should be located right across the VTT output pins (VTT and PGND2) as close as possible to the part to minimize parasitics. The switcher power section should connect directly to the ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). Power components should be placed to minimize loops and reduce losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not use "minimum" land patterns for power components. Minimize trace lengths between the gate drivers and the gates of the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most critical. Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling requirement (and to reduce parasitics) if routed on more than one layer. Current sense connections must always be made using Kelvin connections to ensure an accurate signal. We will examine the SC486 DDR2 reference design used in the Design Procedure section while explaining the layout guidelines in more detail.
VBAT 5VSUS 5VRUN 5VSUS R3 470k R1 R4 10R VDDQ C1 no-pop REF R6 10R R8 23k2 C9 1u C10 no-pop R5 4k64 C2 1u 715k R2 10R 11 3 2 6 R7 10R C3 no-pop R9 0R C11 1n C12 1u 8 9 10 5 4 14 15 12 13 16 17 VBAT
U1 VTTEN VDDQS TON FB REF COMP VTTS VCCA VSSA VTT VTT VTTIN VTTIN PGND2 PGND2 PAD
SC486 PGD EN/PSV
7 1 D1
PGOOD
BST
24
C5 C4 0.1uF R10 13k0 Q1 IRF7811AV L1 Q2 1u5 2n2/50V
C6 0u1/25V
C7 10u/25V
C8 10u/25V
DH ILIM LX
23 21 22
VDDQ + C13 220u/15m + C14 220u/15m
VTT VDDQ C15 10u C16 10u C17 1u
DL VDDP PGND1
19 20 18 C18 1u
FDS6676S
Figure 4: DDR2 Reference Design and Layout Example Sample DDR2 Design Using SC486 VBAT = 9V to 19.2V VDDQ = 1.8V @ (8+2)A VTT = 0.9V @ 2A
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POWER MANAGEMENT
Layout Guidelines (Cont.) The layout can be considered in three parts, the control section referenced to VSSA, the VTT output, and the switcher power section. Looking at the control section first, locate all components referenced to VSSA1 on the schematic and place these components at the chip. Connect VSSA using a wide (>0.020") trace. Very little current flows in the chip ground therefore large areas of copper are not needed. Connect the VSSA pin directly to the thermal pad under the device as the only connection to PGND from VSSA.
5VRUN
R4 VDDQ C1 no-pop REF R5 4k64
10R C2 1u
11 3 2 6 R7 R6 10R 10R C3 no-pop C10 no-pop C11 1n C12 1u 8 9 10 5 4 14 15 12 13 16 17
U1 VTTEN VDDQS TON FB REF COMP VTTS VCCA
SC486 PGD EN/PSV
7 1
BST
24
R8 23k2
DH ILIM
23 21 22
C9 1u
VSSA VTT VTT VTTIN VTTIN PGND2 PGND2 PAD
LX
DL VDDP PGND1
19 20 18 C18 1u
Figure 7: Components Connected to VSSA
Figure 8: Example VSSA 0.020" Trace
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SC486
POWER MANAGEMENT
Layout Guidelines (Cont.) In Figure 8, all components referenced to VSSA have been placed and have been connected using a 0.020" trace. Decoupling capacitor C12 is as close as possible to VCCA and VSSA and the VDDP decoupling capacitor C18 is as close as possible to VDDP and PGND1. The feedback components R5, R8 and C1 along with the VDDQ sense components, R4 and C2 are also located at the chip and the feedback trace from the VDDQ output should route from the top of the output capacitors (C13 and C14) in a quiet layer back to these components. In Figure 8, the VDDQ feedback trace would connect to the red trace.
11 R4 C1 R5 no-pop 4k64 10R C2 1u 6 8 9 10 R8 23k2 5 4 14 15 12 13 16 17 3 2
U1 VTTEN VDDQS TON FB REF COMP VTTS VCCA VSSA VTT VTT VTTIN VTTIN PGND2 PGND2 PAD
SC486 PGD EN/PSV
7 1
BST
24
DH ILIM LX
23 21 22 + C13 220u/15m + VDDQ C14 220u/15m
DL VDDP PGND1
19 20 18
VDDQ FEEDBACK
Figure 9: VDDQ Feedback and Sense Components and Feedback Trace
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SC486
POWER MANAGEMENT
Layout Guidelines (Cont.) Next, looking at the switcher power section, the schematic in Figure 10 below shows the power section for VDDQ:
VBAT 1 2 3 4 Q1 IRF7811AV 8 S D 7 S D 6 S D 5 G D
C5 2n2/50V
C6 0u1/25V
C7 10u/25V
C8 10u/25V
L1 FDS6676S Q2 8 7 6 5 D D D D S S S G 1 2 3 4
1u5 VDDQ + C13 220u/15m + C14 220u/15m
Figure 10: VDDQ Power Section and Input Loop The highest di/dts occur in the input loop (highlighted in red) and thus this should be kept as small as possible. The input capacitors should be placed with the highest frequency capacitors closest to the loop to reduce EMI. Use large copper pours to minimize losses and parasitics. See Figure 11 below for an example.
Figure 11: Example VDDQ Power Section Layout
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SC486
POWER MANAGEMENT
Layout Guidelines (Cont.) Key points for the switcher power section: 1) there should be a very small input loop, well decoupled. 2) the phase node should be a large copper pour, but compact since this is the noisiest node. 3) input power ground and output power ground should not connect directly, but through the ground planes instead. Connecting the control and switcher power sections should be accomplished as follows (see Figure 12 below): 1) Route VDDQ feedback trace in a "quiet" layer away from noise sources. 2) Route DL, DH and LX (low side FET gate drive, high side FET gate drive and phase node) to chip using wide traces with multiple vias if using more than one layer. These connections are to be as short as possible for loop minimization, with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power ground as its return path. LX is the noisiest node in the circuit, switching between VBAT and ground at high frequencies, thus should be kept as short as practical. DH has LX as its return path. 3) BST is also a noisy node and should be kept as short as possible. 4) Connect PGND pins on the chip directly to the VDDP decoupling capacitor and then drop vias directly to the ground plane.
U1 VTTEN VDDQS TON FB REF COMP VTTS VCCA VSSA VTT VTT VTTIN VTTIN PGND2 PGND2 BST 24 Q1 10 5 4 14 15 12 13 16 17 DH ILIM LX 23 21 22 Q2 DL VDDP PGND1 19 20 18 FDS6676S R10 13k0 IRF7811AV L1 1u5 EN/PSV SC486 PGD
11 3 2 6 8 9
7 1
PAD
Figure 12: Connecting Control and Switcher Power Sections Phase nodes (black) to be copper islands (preferred) or wide copper traces. Gate drive traces (red) and phase node traces (blue) to be wide copper traces (L:W < 20:1) and as short as possible, with DL the most critical. Use multiple vias when switching between layers. Locate the current limit resistor (R10) at the chip with a kelvin connection to the phase node.
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POWER MANAGEMENT
Layout Guidelines (Cont.) Next looking at the VTT output:
U1 VTTEN VDDQS TON FB REF COMP VTTS VCCA VSSA VTT VTT VTTIN VTTIN PGND2 PGND2 PAD DL VDDP PGND1 BST 24 SC486 PGD EN/PSV
11 3 2 6 8 9 10 5 4 14 15 12 13 16 17
7 1
DH ILIM LX
23 21 22
VTT VDDQ C15 10u C16 10u C17 1u
19 20 18
Figure 13: VTT Output The output capacitors should be connected right at the chip, on the same side as the chip and right across the pins. The input capacitor may be placed on the opposite side, if desired. See Figure 14 below:
Figure 14: Example VTT Output Component Placement and Starred Ground Output capacitors C15 and C16 are placed across the device pins, and connect to the ground plane using multiple vias. Input capacitor C17 connects directly to the device pins and connects to the ground plane using two vias. Note that PGND1, PGND2 and VSSA all connect to the pad under the device, which should also connect to the ground plane using multiple vias.
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SC486
POWER MANAGEMENT Outline Drawing - MLPQ-24 (4 x 4mm)
A
D
B
DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX
A A1 A2 b D D1 E E1 e L N aaa bbb .031 .035 .039 .000 .001 .002 - (.008) .007 .010 .012 .152 .157 .163 .100 .106 .110 .152 .157 .163 .100 .106 .110 .020 BSC .012 .016 .020 24 .004 .004 0.80 0.90 1.00 0.00 0.02 0.05 - (0.20) 0.18 0.25 0.30 3.85 4.00 4.15 2.55 2.70 2.80 3.85 4.00 4.15 2.55 2.70 2.80 0.50 BSC 0.30 0.40 0.50 24 0.10 0.10
PIN 1 INDICATOR (LASER MARK)
E
A2 A aaa C A1 D1 LxN E/2 E1 2 1 N e D/2 C SEATING PLANE
bxN bbb CAB
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
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SC486
POWER MANAGEMENT Land Pattern - MLPQ-24 (4 x 4mm)
K
(C)
H
G
Z
DIM C G H K P X Y Z
DIMENSIONS INCHES MILLIMETERS (.156) (3.95) 3.10 .122 .106 2.70 .106 2.70 .020 0.50 .010 0.25 .033 0.85 .189 4.80
X P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
2006 Semtech Corp.
26
www.semtech.com

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